Data processing systems often are arranged with a graphics display which provides an optical display of output information for the user. A video random access memory is a basic part of the graphics display arrangement.
In the prior art, the video random access memory includes a serial register to which a row of data from the random access memory array is transferred in preparation for a serial readout operation. The serial register has a number of stages equal in number to the columns in the video random access memory. Each serial register stage includes a tap that can be addressed by the same binary address that is used for addressing the associated column in the video random access memory array.
Address decoding for the video random access memory array columns and the taps of the serial register have been accomplished separately in prior art arrangements. The video random access array columns are selected by decoding an applied binary address into a one out-of-X code, where X equals the number of columns in the array. The desired one column is selected by the active signal in the one-out-of-X code. Serial register taps are selected by decoding an applied initial tap binary address into a code that is applied to a binary counter. When a serial sequence is to be read out of the serial register, the initial tap address and subsequent addresses in the binary counter are incremented for producing a series of successive addresses for the serial register taps. The sequence of binary addresses is decoded into a one-out-of-X code which selects the desired sequence of the serial register taps. Each desired tap is selected by the active signal in the one out of X code.
There are four data lines selected for access at one time. A stages select signal enables data gates between the selected serial register stages and their associated data lines. The enabled data gates allow the data bit stored in each selected serial register stage onto the associated data line. This does not complete the access of the data because a single one of those data bits then is further gated to the output circuitry. The other three data bits may not be gated to the output in sequence following the first data bit.
Since each of the four data lines has a data bit applied when the data gates are enabled, the resulting signals can remain on the data lines when the stages select signal makes a new selection of serial register stages. The newly selected stages also are enabled to apply their stored data bits onto the data lines. Since the data lines are lengthy and have a large number of serial register stages gated to them, there is a large capacitance connected to each data line.
Such capacitance delays decay of the signal representing the first signal on each data line and retards ramp up of the second signal on each data line. Errors can occur in the detection of the data bits if the access operation is run too fast. Also under some circumstances, the data bit residing on the data line when another serial register stage is enabled may overwrite the existing data bit in that serial register stage.